-Reserved Instruction Exception

17.3 TLB Refill Vector Selection

Reserved Instruction Exception

Cause

The Reserved Instruction exception occurs when one of the following conditions occurs:

an attempt is made to execute an instruction with an undefined major opcode (bits 31:26)

an attempt is made to execute a SPECIAL instruction with an undefined minor opcode (bits 5:0)

an attempt is made to execute a REGIMM instruction with an undefined minor opcode (bits 20:16)

an attempt is made to execute 64-bit operations in 32-bit mode when in User or Supervisor modes

an attempt is made to execute a COP1X when the MIPS IV ISA is not enabled

64-bit operations are always valid in Kernel mode regardless of the value of the KX bit in the Status register.

This exception is not maskable.

Processing

The common exception vector is used for this exception, and the RI code in the Cause register is set.

The EPC register contains the address of the reserved instruction unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction.

Servicing

No instructions in the MIPS ISA are currently interpreted. The process executing at the time of this exception is handed a UNIX SIGILL/ILL_RESOP_FAULT (illegal instruction/reserved operand fault) signal. This error is usually fatal.

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